The present invention relates to a method and system for compressing test data used in the testing of logic products such as integrated circuit chips and the like, to economize on the amount of computer memory, disk storage and time required to test such products.
In the testing of devices utilized in computers, such as combinational logic circuit chips and memory arrays, tester devices are used. To test, for example, a combinational logic circuit, a tester applies stimuli to inputs of the chip, and resulting output responses are observed in order to detect faults in an expected performance of the logic circuit. The detected faults may be used to debug the circuit design.
One method of applying test stimuli to a logic circuit includes placing “scan latches” before and after the combinational logic circuits to be tested. In this method, test data is clocked or scanned from a data input pin to a chain of input latches. The test data typically comprises 0s and 1s which may be arranged as a plurality of vectors. The test vector data comprises “care” bits and “non-care” bits. Care bits are bits which are set by test-generating software to target specific or “focal” faults in the logic being tested. Non-care bits are not targeted toward any particular focal fault. A chain of input latches loaded with test vector data may be referred to as a “scan chain.”
According to the method, application of the test vectors to the combinational logic does not begin until all of the input latches are filled using scan chains. Once all the input latches are filled, the test vectors are released and applied to the combinational logic. The combinational logic processes the test vectors and captures the results in latches, and from there the results are scanned to a test output pin where faults may be detected. Advances in computer technology have permitted significant increases in the density with which logic circuits can be packed onto a chip, and accordingly, the number of functions and operations that a chip can perform has increased significantly. Attendant to the increased density and number of logic circuits on a chip, there is an increase in the number, complexity and size of test vectors which need to be applied by a tester to fully verify the chip's operation. Along with the increased volume of test vectors are associated costs in computer resources used in generating and storing the test vectors, and in tester memory and time needed to download test data to the tester.
In view of the foregoing, a method and system for efficiently handling test vector data which addresses the noted concerns is needed.